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fn6004 rev. 3.00 page 1 of 43 july 8, 2005 fn6004 rev. 3.00 july 8, 2005 isl5217 quad programmable up converter datasheet the isl5217 quad programmable upconverter (qpuc) is a qask/fm modulator/fdm upc onverter designed for high dynamic range applications such as cellular basestations. the qpuc combines shaping and inte rpolation filters, a complex modulator, and timing and carrier ncos into a single package. each qpuc can create four fd m channels. multiple qpucs can be cascaded digitally to provide for up to 16 fdm channels in multi-channel applications. the isl5217 supports both vector and fm modulation. in vector modulation mode, the qpuc accept s 16-bit i and q samples to generate virtually any quadrature am or pm modulation format. the qpuc also has two fm modulation modes. in the fm with pulse shaping mode, the 16-bit frequency samples are pulse shaped/bandlimited prior to fm m odulation. no band limiting filter follows the fm modulator. this fm mode is useful for gmsk type modulation formats. in the fm with band limiting filter mode, the 16-bit frequency samples dire ctly drive the fm modulator. the fm modulator output is f iltered to limit the spectral occupancy. this fm mode is useful for analog fm or fsk modulation formats. the qpuc includes an nco driven interpolation filter, which allows the input and output sample rate to have an integer and/or variable relationship. this re-sampling feature simplifies cascading modulators with sample rates that do not have harmonic or integer frequency relationships. the qpuc offers digital output spectral purity that exceeds 100db at the maximum output sa mple rate of 104msps, for input sample rates as high as 6.5msps. a 16-bit microprocesso r compatible interface is used to load configuration and baseband data . a programmable fifo depth interrupt simplifies the interf ace to the i and q input fifos. features ? output sample rates up to 104msps with input data rates up to 6.5msps ? processing capable of >140db sfdr out of band ? vector modulation for supporting is-136, edge, is95, td- scdma, cdma-2000-1x/3x, w-cdma, and umts ? fm modulation for supporting amps, nmt, and gsm ? four completely independent channels on chip, each with programmable 256 tap shaping fir, half-band, and high order interpolation filters ? 16-bit parallel ? processor interface and four independent serial data inputs ? two 20-bit i/o buses and two 20-bit output buses allow cascading multiple devices ? 32-bit programmable carrier nco; 48-bit programmable symbol timing ncos ? dynamic gain profiling and output routing control ? pb-free plus anneal available (rohs compliant) applications ? single or multiple channel digital software radio transmitters (wide-band or narrow-band) ? base station transmitter and smart antennas ? operates with hsp50216 in software radio solutions ? compatible with the hi5960/ isl5961 or hi5828/isl5929 d/a converters block diagram ordering information part number temp range ( o c) package pkg. dwg. # isl5217ki -40 to 85 196 ld bga v196.15x15 isl5217kiz (note) -40 to 85 196 ld bga (pb-free) v196.15x15 ISL5217EVAL1 25 evaluation kit note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free products are msl classified at pb- free peak reflow temperatures that meet or exceed the pb-free requirements of ip c/jedec j std-020. input data parallel host interface shaping intpl filter carrier nco sin cos gain profile iout(19:0) qout(19:0) iin(19:0) configuration and control bus fm mod. sample nco complex mixer p<15:0> a<6:0> {cntrl} i0 q0 i1 q1 i2 q2 i3 q3 4 ch sum 1 cas sum qin(19:0) channel 0 sdb sdc sdd sda channel 1 channel 2 channel 3 2 3 4 i/q half band filter/ i/q i/q i/q i/q gain control i/q ? ? ? ? ? delay sum cas sum
fn6004 rev. 3.00 page 2 of 43 july 8, 2005 isl5217 functional block diagram p<15:0> reset clk a<6:0> wr rd cs rdmode offbin outen<1:0> tritst sdb sdc sdd sda sclkb sclkc sclkd sclka fsrb fsrc fsrd txenb txenc txend txena updb updc updd upda synco uprocessor istrb iout<19:0> qout<19:0> iin<19:0> qin<19:0> tdi tck trst tms tdo jtag isl5217 device channel update<3:0> tx_enable<3:0> <4:0> reset outputmode<1:0> i_strobe_en istrobepolarity outputmode2x cascade_in_enable cascade_delay<1:0> serial interface channel 0 interface interface up 1-7 deep fifo mux fm mod. shaping filter sample nco carrier nco interpolation filter mixer mux mux mux i fifo q fifo limiter i in<15:0> q in<15:0> i in<15:0> q in<15:0> i fm q fm i sf sr<47:0> fid<31:0> intpl phases<1:0> phase offset<1:0> mod. type <1:0> fine coarse carrier frequency<31:0> carrier phase<15:0> 21 21 complex sin<18:0> cos<18:0> gain<11:0> gain profile length<6:0> i<21:0> q<21:0> channel 1 channel 2 channel 3 routebus<15:0> istrobeupdate fsra and timing ch_select<3:0> summer 4 input output_en ch_enable<0> dualquadmode (ch0 and ch2 only) i<21:0> q<21:0> ch_en<2> i<21:0> q<21:0> ch_en<3> i<21:0> q<21:0> ch_en<1> programmable delay tritst_enable_bus<7:0> control output 1 summer 4 input 2 summer 4 input 3 summer 4 input 4 ser._par. routebus_update gain profile band half 20 20 / / / / / / / / / 18 20 16 16 18 bypass phase<3:0> phase<11:0> / / gain control control routing isl5217 fn6004 rev. 3.00 page 3 of 43 july 8, 2005 pinout 196 ldbga top view k j h g f e d c b a 123456789 11 10 l m n vccio iin1 12 txena 13 14 iin15 gnd iin7 iin3 sdb sdd qin1 iin16 qin4 gnd sclkc iin17 iin11 qin10 rdmode qin2 iin18 sclkd qin8 qin6 qin15 updd gnd qin12 fsrc iin19 fsrd tdi cs tck gnd rd qin17 tms clk a4 a2 qin19 p0 istrb gnd a5 tritst p2 gnd reset qout4 iout19 qout6 p4 qout13 qout10 qout0 qout3 gnd p14 p8 qout15 qout12 qout9 iout7 iout1 vccio iout3 iout11 vccio gnd iout9 vccio iout0 iout2 iout4 p15 p12 p11 iout13 iout12 iout10 gnd iout8 iout6 p sda iin0 iin13 iin2 sdc txenb sclka iin12 iin10 iin8 iin6 iin4 power pin ground pin signal pin thermal ball nc (no connection) qout19 qin18 qin16 fsrb a3 iout14 iout15 iout16 iout5 qout16 iout17 iout18 p6 p3 p5 vccc qin13 iin14 txenc sclkb upda qout1 qin11 gnd p13 p10 p9 gnd qout5 qout7 qout14 qout11 qout8 qout2 gnd gnd vccio vccc vccc vccc p7 vccc qout17 qout18 offbin tdo trst outen0 outen1 fsra synco a0 a1 a6 qin3 qin5 qin9 qin7 vccc p1 gnd vccc vccc wr gnd qin14 updc vccc gnd vccio vccc vccio vccio gnd gnd iin5 updb txend qin0 iin9 vccc gnd vccc gnd note: thermal balls should be connected to the ground plane. isl5217 fn6004 rev. 3.00 page 4 of 43 july 8, 2005 pin descriptions (all signals are active high unless ot herwise stated) name type description power supply vccc - positive device core power supply voltage, 2.5v ? 0.125v. vccio - positive device input/out put power supply voltage, 3.3v ? 0.165v. gnd - ground, 0v microprocessor interface and control clk i input clock. all processing in t he isl5217 occurs on the rising edge of clk. reset i reset. (active low). asserting reset will clear all configuration registers to t heir default values, halting all processing. p<15:0> i/o data bus. bit 15 is the msb. a<6:0> i address bus. bit 6 is the msb. cs i chip select. (active low). e nables device to respond to ? p access. note: see appendix a, errata sheet. rdmode i read mode. read mode selects the read/write mode for the microprocessor interface. when low the device is configured for separate rd and wr strobe inputs. when high the device is configured for a common read/write and data strobe inputs. internally pulled down. wr i write strobe, (active low). dual function input. the input is configured for write strobe when rdmode is low. when rdmode is high the input is configured for data strobe. write strobe. the data on p<15:0> is written to the des tination selected by a<6:0> on the rising edge of wr when cs is asserted (low). data strobe. the data on p<15:0> is written to the destinat ion selected by a<6:0> on the rising edge of data strobe when rd is low and cs is asserted (low) or read from the address selected by a<6:0> placed on p<15:0> when rd is high and cs is asserted (low). rd i read strobe (active low). dual function input. the i nput is configured for read strobe when rdmode is low. when rdmode is high the input is configured for read/write strobe. read strobe. the data at the address selected by a(6:0) is placed on p<15:0> when rd is asserted (low) and cs is asserted (low). read/write strobe. determines the type of ? p access. offbin i offset binary. when set to 1, the output data bus format is offset binary. when set to 0 the output data bus format is 2?s complement. outen<1:0> i output three-state control. outen<1:0> is decoded to provide three-state control of the output data buses. when tritst is asserted, the three-state control divides the 80 -bit output into eight groups of 10-bits each. when tritst is deasserted, the three-state control operates on t he 20-bit real and imaginary cascade out data buses. tritst i tester three-state control. this signal determines how the outen<1:0> is decoded to provide the necessary three-state controls when in normal or test er applications. set low for normal operation. serial data / synchronization and fifo status sda, sdb, sdc, sdd i serial data a-d. (sdx) serial data input for the i and q vectors. the processing channel selected for this data will shift the data in on the rising edge of its serial tx cloc k. the data vectors are shifted in with the msb first. sclka, sclkb, sclkc, sclkd o serial clk a-d. (sclkx ) dual function output. the output is serial clk when symbol data is input through the serial data port. when symbol data is input through the ? p port the output is sample clk 0-3. the polarity of sclkx is programmable. serial clock. programmable rate clock signal provided to the data source to shift serial data out. programmed rates can be clk/(1-32), or 32x sample clock. see c ontrol word 0x17, bit 15 for shut-off conditioning. sample clk. signal provided to the data source to indica te when data is being transferred from the fifo to the shaping filter. the sample clk output is generated by the sample rate nco and has approximately 50% duty cycle. the sample is taken on the high-to-low transition. fsra, fsrb, fsrc, fsrd o frame strobe a-d. (fsrx ) multiple function output. when control word 0x0c, bit 11 is set to zero, the output is frame strobe when symbol data is input through the serial data port. when symbol data is input through the ? p port the output is fifo ready 0-3. when control word 0x0c, bit 11 is set to one, the setting of the fsrmode<1:0> bits in indirect address 0x 407 determine the output. the polarity of fsrx is programmable. frame strobe. signal provided to the data source to initiate a serial word transfer. alternatively selectable through serial control 0x11, bit 14 to be epoch frame str obe. epoch is a pre-carry out of the fixed integer divider instead of the serial frame strobe. the epoch pre-carry out is six clocks ahead of the true carry out and can be used to synchronize fixed integer dividers of other devices . see control word 0x17, bi t 15 for shut-off conditioning. fifo ready. indicates the i and q fifo poi nter is less than the programmed fifo depth. updx or txenx: when 0x0c, bit 11 is set to one, and fsrmode<1 :0> is set to 10, the internal channel updx is output. when 0x0c, bit 11 is set to one, and fsrmode< 1:0> is set to 11, the internal channel txenx is output. see table 43 for additional details. isl5217 fn6004 rev. 3.00 page 5 of 43 july 8, 2005 txena, txenb, txenc, txend i transmit enable a-d. (txenx ) the processing channel selected for th is enable will forc e a channel flush (conditioned by control word 0x0c, bit 2), clear the dat a rams, and update the selected configuration registers upon assertion. no additional requests fo r serial data will be made when txenx is deasserted, unl ess conditioned by control word 0x0c, bit 3. the polarity of txenx is programmable. optionally, txenx can be internally generated with a programmable duty cycle. two different programmable txenx cycles can be prog rammed and toggled between based on prog rammed cycle length. see control word 0x0c, bit 11 and table 43 for addi tional details. upda, updb, updc, updd i update a-d. (updx ) the processing channel selected for this input updat es the selected configuration registers, if the associated update mask bit is set. the polarity of updx is programmable. synco o synchronization output. the processing of multiple isl5217 devices can be synchronized through software by connecting the synco of the master isl5217 device to an updx pin of the isl5217 slaves. the polarity of synco is programmable. modulated data (80) iout(19:0) o output data bus a (19:0). output bus a contains the digital modulated quc output samples from output summer/formatter 1. the samples are updated on the rising edge of the clk. bit <19> is the msb. qout(19:0) o output data bus b (19:0). the output bus contai ns the digital modulated quc output samples from output summer/formatter 2. the samples are updated on the rising edge of the clk. bit <19> is the msb. iin(19:0) i/o i cascade in (19:0) or output bus c. dual functi on i/o bus. the bus is configured for input when the output mode is cascade in. the bus is configured for output for all other output modes. i cascade in. input bus allows multiple parts to be ca scaded by routing the digital modulated signal i cas out, (bus a), from one quc into output summer/formatter 1 of a second quc. i cas in (19:0) is in 2?s complement format and is sampled on the rising edge of clk. bit<19> is the msb. output data bus c. the output bus contains the digital modulated quc output samples from output summer/formatter 3. the samples are updated on the rising edge of the clk. bit <19> is the msb. qin(19:0) i/o q cascade in (19:0) or output data bus d. dual function i/o bus. the bus is configured for input when the output mode is cascade in. the bus is configured for output for all other output modes. q cascade in. input bus allows multiple parts to be ca scaded by routing the digital modulated signal q cas out, (bus b), from one quc into output summer/formatter 2 of a second quc. q cas in (19:0) is in 2?s complement format and is sampled on the rising edge of clk. bit<19> is the msb. output data bus d. the output bus contains the digital modulated quc output samples from output summer/formatter 4. the samples are updated on the rising edge of the clk. bit <19> is the msb. istrb o i data strobe. (active high). used in the muxed i/q mode. when asserted, the output data buses contain valid i data. jtag test access port tms i jtag test mode select. internally pulled up. tdi i jtag test data in. internally pulled up. tck i jtag test clock. trst i jtag test reset (active low). internal ly pulled-up. this pin should be driven by the jtag logic to obtain a tap controller reset, or if jtag is not utilized, this pi n should be tied to ground for normal operation. as recommended in the 1149.1 standard documentation the trst test pin should be made active soon after power-up to guarantee a known state within the tap logic on the isl5217. this avoids potential damage due to signal contention at the circuit?s inputs and outputs. tdo o jtag test data out. pin descriptions (all signals are active high unless ot herwise stated) (continued) name type description isl5217 fn6004 rev. 3.00 page 6 of 43 july 8, 2005 functional description the isl5217 quad programmable upconverter (qpuc) converts digital baseband data into modulated or frequency translated digital samples. the qpuc can be configured to create any quadrature amplitu de shift-keyed (qask) data modulated signal, including qpsk, bpsk, and m-ary qam. the qpuc can also be configured to create both shaped and unfiltered fm signals. a minimum of 16 bits of resolution is maintained throughout the internal processing. the qpuc is configured via the microprocessor data bus, using the a<6:0> address bus, p<15:0> data bus, rd , wr and cs control signals. configuration data that is loaded via this bus includes the individual channel?s 48-bit sample rate nco center frequency, the 32 -bit carrier nco center frequency, the device modulation format, gain control, input mode control, reset control and sync control. the i and q baseband channels each have a 256 tap fir filter whose coefficients and configuration are also programmed via the ? p interface. similarly, the control signals for the i and q channel interpolation filters are programmed via the ? p interface. discussion in the following sections utilizes the register definitions for channel 0. channels 1-3 are similarly configured in accordance with the table 10 memory map. data input the i/q sample pairs can be in put serially through 1 of 4 serial interfaces or in parallel through the ? p addressable registers as shown in figure 1. serial the serial mode allows the device to shift the i and q samples serially into the fifo holding registers. the serial input format is selected when serial control (0x11, bit 15) is high. the serial interface is three-wire interface controlled by the channel. the serial clock and frame strobe are driven by the channel to clock the serial data from the source into the serial data port. the serial clock can operate at the clock rate, at a divided clock rate, or be driven at 32x the sample clock rate. serial control (0x11, bits 13:8) configure the serial clock. in the 32x mode, back to back 16-bit serial transfers can occur by setting control word (0x17, bits 14:13) both high. t he serial process begins with the first serial clock after the star t of a sample clock. the frame strobe is asserted for one serial clock and starts the i and q time slot counters. the txenx pin or main control (0x0c, bit 0) s/w tx enable must be asserted to enable the frame strobe out. additional requests for serial data, with txenx de- asserted, are controlled by bit 3 of control word 0x0c. the serial interface may be programmed to be dependent or independent of txenx control. the i and q time slot counters, programmed through 0x12, bits 9:0 and 0x13, bi ts 9:0, control the duration of the serial to parallel conversion of the serial data input. the counters are loaded to count the number of serial clocks from the frame strobe to shift in the last data bit of that sample. the time slot counters are 10-bits to allow multiple channels to share a common serial data input. the msb is always shifted first, but the order of the i and q serial data is flexible due to the variability of the time slot counters. the received serial word is msb justified prior to loading into the fifo holding register based on the serial word length, programed through serial control (0x11, bits 3:2) to 4, 8, 12, or 16 bits. although each channel has contro l of a serial interface it may select serial data from one of the other interfaces. serial control (0x11, bits 1:0) selects 1 of 4 serial data ports for the channel. the serial data transfer format is shown in figure 2. the ability to select the serial input source allows multiple qpucs to share a single microprocessor interface with their processing synchronized thro ugh the master qpuc synco being tied to the slave device updx . conversely, multiple figure 1. single channel data input path 4:1 mux sdb sdc sdd sda 2:1 mux 0x11, 1:0 serial to parallel 0x13, 9:0 0x12, 9:0 2:1 mux q sample (15:0) i sample (15:0) 0x1, 15:0 0x0, 15:0 p<15:0> a<6:0> 0x11, 15 channel ? p interface 0x11, 3:2 parallel figure 2. serial data transfer updx txenx fsrbx sdx sclkx inactive dont care q isl5217 fn6004 rev. 3.00 page 7 of 43 july 8, 2005 microprocessors can share a single qpuc as shown in figure 3. parallel the parallel mode allows the ? p to write the i and q samples directly to the fifo holding registers. the parallel input format is selected when serial control (0x11, bit 15) is low. the normal ? p write order is the q sample, control word 0x1, followed by the i sample, control word 0x0. writing to control word 0x0 generates the update strobe to move the data from the fifo holding register into the first location of the i/q fifo. the first location of the i/q fifo is available for read back. the ? p can perform back-to-back write accesses to control words 0x1 and 0x0, but must maintain four f clk periods between accesses to the same address. this limits the maximum ? p write access rate for an i/ q sample pair to 104mhz/4 = 26mhz. the read/write format for a parallel data transfer is shown in figure 4 fifo the fifo provides the interf ace and data storage between the input source and the shapin g filter or fm modulator. the fifo can hold up to seven i /q sample pairs. the block diagram is shown in figure 6. the input source to the fifo is selected by serial control (15). the fifo pointer is incremented every time data is written into the fifo. the trans ferring of data into the fifo does not occur until both i and q have been received when the sample data is input in a serial fashion. when the sample data is input in a parallel fashion, the transferring of data into the fifo occurs when the ? p writes to control word 0 (i data). while the input source determines the write rate, the shaping filter determines t he read rate. the maximum read rate occurs when the shaping filter constraints for data span (ds) and interpolation phases (ip) equal four. for a clock rate of 104mhz, the maximum read rate is determined by f clk /(ds)(ip), which is 104mhz/16 = 6.5mhz. see the shaping filter section for more details. when the shaping filter requires another data sample, a request is made to the fifo for data and the fifo pointer is decremented. figure 5 indi cates the timing of a request for data from the shaping filter to the actual appearance of data at the fifo output. an ?empty? fifo detection causes zero valued data to be entered into the shaping filter. the fifo can be forced to enter zero valued data by setting the on-line mode to false. the on-line mode is enabled by main control (0xc, bit 6). a ?full? fifo detection prevents data from being pushed out of the fifo before the filter requests it. writing to a full fifo is treated as an error condition that will result in a soft reset of the channel to prevent transmission of erroneous data ov er the air. the full fifo channel reset can be disabled by control word 0x0c, bit 1. a programmable fifo depth threshold sets when the fifordy signal is asserted, alerting the data source that more data is required. the fifordy signal assists the data source in maintaining the desired fifo data depth. the data fifo depth threshold for both i and q inputs is set by main control (0xc, bits 10:8). the sample clk may be used instead of fifordy to indicate when data has been transferred from the fifo to the shaping filter. see the pin description table for additional details and figure 5 for the input data latency. figure 3. multiple configurations ? p sclkx fsrx sdx master qpuc isl5217 synco slave qpuc isl5217 updx slave qpuc isl5217 slave qpuc isl5217 updx updx ? p sclkx fsrx sdx channel 0 qpuc isl5217 ? p sclkx fsrx sdx ? p sclkx fsrx sdx ? p sclkx fsrx sdx channel 1 channel 2 channel 3 updx rdmode rd wr a<6:0> clk 01 figure 4. parallel data transfer p<15:0> 00 01 00 q i q i 01 00 q i isl5217 fn6004 rev. 3.00 page 8 of 43 july 8, 2005 data modulation path three data path options are provided, one for each modulation format. the modulation format is selected using fir control (0xd, 3:2). the modulation paths are defined in the following subsections. figure 5. fifo data and enable timing clk wr dly data dff 1 dff 2 dff 3 dff 4 reg1 fifordy write_fifo 1234 fifo needs more data fifo needs more data figure 6. i and q fifo block diagram zeros comp dff comp 0xc, 10:8 8:1 mux wr a(000) write_fifo write_fifo a(2:0) ififo(15:0) qfifo(15:0) fifordy dff1 dff2 dff3 dff4 0 1 fm enabled ? all registers are clocked at clk unless shown otherwise. 2:1 mux serial_write_to_fifo clock synchronization almost empty threshold 4:1 mux sdb sdc sdd sda 2:1 mux 0x11, 1:0 serial to parallel 0x13, 9:0 0x12, 9:0 2:1 mux q sample (15:0) i sample (15:0) 0x1, 15:0 0x0, 15:0 p<15:0> a<6:0> 0x11, 15 channel ? p interface 0x11, 3:2 parallel r e g > r e g > r e g > r e g > r e g > r e g > r e g > 8:1 mux r e g > r e g > r e g > r e g > r e g > r e g > r e g > r e g > r e g > r e g > r e g > 0x11, 15 isl5217 fn6004 rev. 3.00 page 9 of 43 july 8, 2005 modulation mode 00 - qask this modulation mode configures the qpuc as a bpsk, qpsk, oqpsk, msk or m-qa m modulator. the block diagram is shown in figure 7. the data fifo outputs are routed to the shaping filters. here the samples are interpolated by 4, 8, or 16 and shaped using a fir filter with up to a 256 taps. the filter impulse response can span 4-16 input samples. a half (input) sample delay can be inserted in the i/q path after the fir and is enabled through main control (0xc, bit 13). the 20-bit output of the s haping filter is routed through a gain adjust mu ltiplier controlled by 0x0a, bits 11:0 and into the interpol ation filter. the interpolation filter interpolates by a factor set in the resampling nco with the interpolation phases contro lled by 0xd, bits 1:0. the output of the interpolation filt er is at the master clock frequency, clk. the samples are then mixed with the carrier l.o. for quadrature upconver sion. the output is then summed with the cascade input signal, saturated (in the case of overflow), a nd formatted for output. modulation mode 01 - fm with bandlimiting filter this mode configures the qpuc as an fm modulator with post-modulation filter ing. the block diagram is shown in figure 8. this mode provides for fsk and fm modulation schemes. in this mode, the i input samples drive the frequency control section of a quadrature nco to produce a zero if fm signal. the 16-bit fm quadrature signals are then routed to the shaping fi r filter and into the interpolation filter for bandlimiting and interpolation up to the master clock rate. the quadrature filtered fm signals are then upconverted to the carrier frequency by the carrier nco and mixers. the output is then summed with the cascade input signal, saturated (in the case of overflow), and formatted for output. note that pulse shaping in this mode must be provided prior to the qpuc. modulation mode 10 - fm with pulse shaping this mode configures the qpuc as a fm modulator with pre-modulation baseband pulse shaping. the block diagram is shown in figure 9. the data from the fifo (i channel only) is routed to the fir shaping filter. the fir shaping filter output drives the frequency co ntrol section of a quadrature nco to produce a zero if fm signal. these 18-bit fm modulated quadrature samples are then up sampled in the interpolation filter to the output sample rate. the baseband modulated signal is then upconverted to the carrier frequency by the carrier nco and mixers. the output is then summed with the cascade input signal, saturated, and formatted for output. in mode 10, the amplitude out of the shaping filter needs to be limited in order to prevent frequency excursions that cannot be filtered out in the interpolation filter. note: the quality of the fm signal is affected by the amplitude slew rate out of the shaping filter. as a rule of thumb, limiting this slew rate to less than 1/8 the sample rate will minimize this distortion. fm modulator the fm modulator provides for frequency modulation of the carrier center frequency by the qpuc input data. the fm modulator is driven either dire ctly by the qpuc i input (mode 01) or by the output of the fi r shaping filter (mode 10). the input data to the fm modu lator, is defined as d ? (n)/dt, where ? (nt) is the phase of a theo retical sinusoid described by: the block diagram is shown in figure 10. the input to the fm modulator, d ? (n)/dt, is integrated via the nco accumulator. the nco accumulator output represents phase and is used to address a sin/cos generator, synthesizing a sinusoid of the form described in equation 1. the phase accumulator feedback of the nco is 20 bits and 18 bits of the phase word are routed to the sin/cos generator. eighteen bits of amplitude are provided on the sine and cosine outputs. the transfer function of the fm modulator is defined by the change in degrees per sample value, d ? (nt)/dt, where d ? (nt)/dt is a 16-bit, twos complement, fractionally notated frequency control word with a range from -f samp /2 to +f samp /2. f samp is defined as the sample rate into the fm gain profile to halfband shaping filter i figure 7. qask q gain profile to half band fm modulator i shaping filter figure 8. fm with bandlimiting gain profile to half band shaping filter i figure 9. fm with pulse shaping fm modulator ?? a (cos ? nt ??? + j sin ? nt ?? ?? ); a ? 1 in modulator ? = (eq. 1) sin/cos rom mode d ? (nt)/dt ? (nt) cos[ ? (nt)] figure 10. fm modulator block diagram sin[ ? (nt)] 16 or 20 20 18 18 ? 01 or 10 r e g > fm isl5217 fn6004 rev. 3.00 page 10 of 43 july 8, 2005 modulator. the maximum phase step that can occur in one clock is ? 180 degrees. table 1 provides the change in phase weighting of the input bits. shaping filter the shaping filter provides the necessary pulse shaping required on the input data to implement various qask and shaped fm modulation formats. two identical shaping filters (one each for the i and q pat hs) are provided. the shaping filter architecture uses a nco controlled interpolating fir, capable of 4, 8, or 16 interp olation phases. the number of interpolation phases, (ip) is loaded into fir control (0xd, bits 1:0). the span of the impulse response of the polyphase filter can vary from 4-16 data samples. the desired sample data span, (ds) value minus one is loaded into fir control (0xd, bits 7:4). thus, the required number of coefficients (or filter span) becomes: the interpolation phase also determines the rate to compute a polyphase output by selecting the appropriate timing from the sample rate nco to drive the shaping filter at 4x, 8x, or 16x the input sample rate. the data span selects the number of samples to convolve. each convolution requires ds reference clocks for each phase of the f ilter. an output is calculated (ip) times for each input sample. to allow sufficient processing time for each output, the reference clock must be as follows: conversely, the input sample rate requires: where f clk is the frequency of the reference clock, ip is the shaping filter interpolate rate; and ds is the number of data samples in the filter span. for example, if f clk = 104mhz, the filter span is 16 samples, and the interpolation rate is 16, then the maximum inpu t sample rate, f s is 104/256 = 406.25khz. table 2 shows several examples of calculations for fir input sample rates based on master reference clock rate, number of data samples, and interpolation rate. the data exits the shaping filters at the interpolated rate. the shaping filters have programmable coefficients which must be loaded via the microprocessor interface. the qpuc supports loading coefficients fo r two shaping f ilters, with fir control (0xd, bit 8) selecting the active filter. the i and q shaping filters are identical and may be loaded simultaneously or separately, allowing for different gains and responses through the filter if desired. because 16 interpolation phases are possible, the coefficients are structured in sets of 16, one set for each phase of the shaping filter. the convolution algorithm sequentially steps through each of these phases, beginning with phase 0. the coefficients for the shaping filters are generated by designing the prototype filter at the interpolated rate. the coefficients are then divided into interpolation phases by taking every n th tap of the prototype filter and storing the coefficien t as an element of a coefficient set. the ip value determines the addressing interval through the prototype filt er to create the coefficient sets for the filter phases. the first coefficient set begins at address 0. the next coefficient set begins at address 1 and continues in a like manner for the remaining coefficient sets. for a 16 tap, interpolate-by-4 filter, the ca lculations for filter 1 are: polyphase output 0 = (c0*d[n] ) + (c4*d[n-1]) + (c8*d[n-2]) + (c12*d[n-3]) polyphase output 1 = (c1*d[n] ) + (c5*d[n-1]) + (c9*d[n-2]) + (c13*d[n-3]) polyphase output 2 = (c2*d[n]) + (c6*d[n-1]) + (c10*d[n-2]) + (c14*d[n-3]) polyphase output 3 = (c3*d[n]) + (c7*d[n-1]) + (c11*d[n-2]) + (c15*d[n-3]) if fir control (8) is set the calculations for filter 2 are: polyphase output 0 = (d0*d[n] ) + (d4*d[n-1]) + (d8*d[n-2]) + (d12*d[n-3]) table 1. phase weighting d ? (nt)/dt degrees/sample 1000 0000 0000 0000 -180 0000 0000 0000 0000 0 0111 1111 1111 1111 ~+180 # coefficients = (ds)(ip) (eq. 2) clk ds ?? ip ?? f s ?? ? (eq. 3) f s f clk [ip ?? ? ds ??? ? (eq. 4) table 2. example calculations example f clk ds ip max f s 1 104mhz 16 16 104/256 = 406.25khz 2 104mhz 16 8 104/128 = 812.5khz 3 104mhz 16 4 104/64 = 1.625mhz 4 104mhz 10 4 104/40 = 2.600mhz 5 104mhz 8 4 104/32 = 3.250mhz 6 104mhz 4 4 104/16 = 6.500mhz table 3. fir controls ip starting address w/fir control (8) = 0 starting address w/fir control (8) = 1 40 8 80 8 16 0 128 isl5217 fn6004 rev. 3.00 page 11 of 43 july 8, 2005 polyphase output 1 = (d1*d[n]) + (d5*d[n-1]) + (d9*d[n-2]) + (d13*d[n-3]) polyphase output 2 = (d2*d[n]) + (d6*d[n-1]) + (d10*d[n-2]) + (d14*d[n-3]) polyphase output 3 = (d3*d[n]) + (d7*d[n-1]) + (d11*d[n-2]) + (d15*d[n-3]) table 4 details the coefficient address allocation for the previous example. the interpol ation phase is on the left and the data span is across the top. the coefficient ram address followed by the coefficient term is listed in the table?s cell. table 49 details the coefficient address locations through 255. the loading options are programmable including read back modes and are discussed in detail in the ?microprocessor interface? section. both 16-bit 2?s complement and 24-bit floating point format are allowed. the 2?s complement coefficient format of valid digital values ranges from 0x8001 to 0x7fff. the value 8000 is not allowed. the 24-bit floating point (20-bit mantissa with 4-bit exponent) mode allows an exponent range from 0 to 15. an exponent of 0 indicates multiplication of the coefficient by 2 0 , and an exponent of 1 is 2 -1 , down to a value of 15 being 2 -15 . the default mode is 2?s complement, with 24-bit fl oating point mode enabled by setting control word (0x17, bit 12). the gain through the filter is: a = (sum of coefficients) / interpolation rate. the shaping filter contains satura tion logic in the event that the final output peaks over +/ - 1.0. when using quadrature modulation, saturation/overflow can occur when the input values for i and q exceed 0.707 peak. the shaping filter coefficients may need to be reduced from full scale to prevent saturation. gain profile the overall channel gain is controlled by both a gain profile stage and a gain control stage, which provide identical scaling for the i and q upconverted data. the gain profile stage allows transmit ramp-up and quench fading, to control the sidelobe profile in burst mode. this is implemented through user control of the rise and fall transitions utilizing a gain profile memory. the gain profile memory is a 128 x 12 bit ram which is loaded with the desired scaling coefficient s via indirect addressing of memory spaces 0x000-0x07f. the pulse shaping is implemented by linearly multiply ing the programmed coefficient by the shaping filter outputs at the f s *ip, or coarse phase rate. the gain profile is enabled by fi r control (0xd, bit 15), with the ram address pointer being reset to zero on assertion of the gain profile enable. control of the pulse shaping is based on txenx , as the txenx rising edge causes the ram pointer to begin stepping through the profile until the ram pointer matches the gain profile length programed into control word (0x0b, bits 6:0). the falling edge of txenx reverses the process and the ram pointer begins decrementing until it reaches zero. the gain process is symmetric with respect to the rising or falling edges of txenx . the latency through the gain profile block is set by cont rol word (0x0b, bits 8:7) where bit 8 bypasses all latency alignment circuitry and uses txenx as input to the channel. setting control word (0x0b, bit 7) removes two edge latencies from the delay path and should be combined with selection of ds = 3, ip = 4 in order to have perfect symmetry through the gain profile block. the memory coefficients may be loaded without taking the channel off-line. this is implemented by setting the gain profile hold bit in control word (0x0c, bit 14) which holds the last gain value and provides access to the memory. the gain profile coefficients are programmed as unsigned values: bit weight 2 0 .2 -1 2 -2 ... 2 -11 maximum 0x800 = 1.0 0x001 = 2 -11 minimum 0x000 = 0.0 table 4. address allocation ds [n] ds [n-1] ds [n-2] ds [n-3] ip0 0 co 16c4 32c8 48c12 ? ip1 1 c1 17c5 33c9 49c13 ? ip2 2 c2 18c6 34c10 50c14 ? ip3 3 c3 19c7 35c11 51c15 ? ip4 4203652? ip5 5213753? ip6 6223854? ip7 7233955? ip8 8 d0 24d4 40d8 56d12 ? ip9 9 d1 25d5 41d9 57d13 ? ip10 10 d2 26 d6 42 d10 58 d14 ? ip11 11 d3 27 d7 43 d11 59 d15 ? ip12 12 28 44 60 ? ip13 13 29 45 61 ? ip14 14 30 46 62 ? ip15 15 31 47 63 ? isl5217 fn6004 rev. 3.00 page 12 of 43 july 8, 2005 gain control the gain control is implemented through a scaling multiplier followed by a scaling shift. the combination of the multiplier and shifter provide the final output gain of the channel. gain adjustment can vary from -0.0026 to -144 dbfs. given a desired attenuation, the scaling multiplier value, gain mult (11:0) can be calculated by the following equation. gain mult (11:0) = int [10 |(gain(db)| / 20 ) 2 12 ] where int[x] is the integer part of the real number x. table 5 details a few scaling multiplier values and their associated attenuations. given a desired attenuation, the shifting value gain shift (2:0) can be determined by a table look-up. refer to table 6. the gain control is loaded into control word 0xa. 0xa, bits 14:12 = gain shift (2:0) 0xa, bits 11:0 = gain mult (11:0) sampling nco the sample rate nco provides the sample clk and sample clock phase information to the data input fifo?s, the shaping filters and the interpolation filters. the input sample rate is set by the sample cloc k. the sample clock is the msb of the nco accumulator and controls the movement of sample data from the user to the shaping filters. the coarse phase of the nco accumulator controls the processing of the shaping filter at 4x, 8x, or 16x the sample clock rate. the fine phase of the nco accumulator controls the processing of the interpolation filter as it re-s amples the data from the shaping filter to the clock rate. the block diagram is shown in figure 11. the sample frequency, sf, is set with 48-bit resolution. the lsb is f clk /2 48 . the internal accumulator re solution is 48 bits. given a desired sample frequency, f s, the value for sf(47:0) can be calculated by the following equation. sf (47:0) = int [(f s / f clk ) * 2 48 ] the sample frequency, sf(47:0) is loaded 16 bits at a time into control words 4, 5, and 6. 0x4, bits 15:0 = sf (47:32) 0x5, bits 15:0 = sf (31:16) 0x6, bits 15:0 = sf (15:0) the output of the phase accumu lator can be offset by phase increments of 90 degrees without affecting the operation of the phase accumulator. the desired of fset increment is loaded into fir control (0xd, bits 11:10). since it is not possible to repr esent all frequencies exactly with an nco, the phase accumulator length has been extended to minimize the effect of phase error accumulation. at an update rate of 1mhz, half an lsb of error in loading the 48-bit accumulator is 1.8e-9. the accumulated phase error after 1 year is 0.056 of a bit. leap counter in addition to lengthening the nco accumulator, a 32-bit counter is available for realizing fixed integer interpolation rates. the carry-out of the fixe d integer counter can be used to clear the coarse and/or fine phase of the sample rate nco. the fixed integer counter also provides a precarry-out that can be used to synchronize fixed integer counters in other devices. the fixed integer counter is enabled by fir control (0xd, bit 12). in programming the fid to clear the nco accumulator, consideration must be provi ded to ensure that fid is programmed to clear the error term only when the desired error term should have been zero with an integer multiple of the symbol rate. selecting gsm as an example, the fid should clear the nco accumulator every third multiple of the symbol rate or every 270833.333 * 3 sa mple clocks, as the error term should only be zeroed during integer multiples of the symbol table 5. scaling gain attenuation gain mult (0xa, 11:0) gain (dbfs) scaling gain (v out /v in )% 1111 1111 1111 -0.0026 99.97 1000 0000 0000 -6.021 50.0 0100 0000 0000 -12.041 25.0 0010 0000 0000 -18.062 12.5 0001 0000 0000 -24.082 6.25 0000 1000 0000 -30.103 3.125 0000 0100 0000 -36.124 1.5625 0000 0010 0000 -42.144 0.78125 0000 0001 0000 -48.165 0.39062 0000 0000 1000 -54.186 0.19531 0000 0000 0100 -60.205 0.097656 0000 0000 0010 -66.226 0.04828 0000 0000 0001 -72.247 0.02441 table 6. gain shift values gain shift (2:0) gain (dbfs) scale by scaling gain (v out /v in )% 000 -72.247 4096 0.02441 001 -48.165 256 0.39062 010 -30.103 32 3.125 011 -24.082 16 6.25 100 -18.062 8 12.5 101 -12.041 4 25.0 110 -6.021 2 50.0 111 0 1 100.0 isl5217 fn6004 rev. 3.00 page 13 of 43 july 8, 2005 rate. this would clear the nco accumulator every 3 seconds or at a 1/3 hz rate. the fr equency of the fid carryout can range from fclk to fclk/2^32. the value of fid is determined from: fid (31:0) = [(fclk / fco)] where fco is the desired frequency of the carryout, which in the previous example is 1/3 hz and the fclk is and integer multiple of the sample frequen cy, say 65mhz. the resultant value for the fid would be (65mhz/1/3hz) or 195e6. the programmed integer values for the fid are loaded 16 bits at a time into control words 2 and 3. 0x2, bits 15:0 = fid (31:16) 0x3, bits 15:0 = fid (15:0) loading 195e6 into the fid would result in 0x2, being 0x0b9f, and 0x3 being 0x76c0. fixed coefficient 11-tap interpolating half-band following the post-fir gain profile block is a fixed coefficient 11-tap interpolate by 2 half-ban d filter. the default mode is to bypass the filter with the sett ing of control word 0x0d, bit 9 enabling the filter. if bypassed, the data to the filter is zeroed which reduces power consumption. the halfband filter coefficients are: 3, 0, -25, 0, 150, 2 56, 150, 0, -25, 0, 3 the output of this filter is ro unded to 20-bits. the output is checked for saturation and limited if necessary. the data exits the halfband filter as a parallel i<20:0> and q<20:0> data stream at the rate of fs*ip*2. figure 12 shows the frequency response of the half-band filter. interpolation filter the shaped sample data is input to the interpolating filter at the interpolation rate. the inte rpolator filter resamples the shaped i and q data to establish the final output sample rate of the channel. the output sample rate is always the clock rate. the interpolator uses the fine phase values from the symbol rate nco to compute the fine interpolated samples at the clock rate. the number of interpolated samples is set by the following ratio: n is = f clk / f s / ip. the nulls in the interpolation filter frequency response align with the interpolation images of the shaping filter. the impulse response of the inter polation filter is shown in figures 13a through 13c for varying interpolation ratios. 12 46 48 syncin wr cw3 sample frequency 2 zero shifter ip(1:0) fine phase coarse phase sampck (msb) syncsel en ? all registers are clocked at clk 4, 3, or 2 ? reg > reg > reg < 0 1 mux ennco (carrier nco) acc start gen edge reset gen edge wr cw21 rst r e g > r e g > figure 11. re-sampling nco block diagram figure 13a. interpolation filter impulse response l = 16; fout = 4096 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -140 -120 -100 -80 -60 -40 -20 0 1 2 5 0 $ / , = ( ' ) 5 ( 4 8 ( 1 & |